1. Field of the Invention
The present invention relates in general to semiconductor memory devices and in more particular to dynamic random-access memory (DRAM) devices of the type employing an array of one-transistor memory cells. The invention also relates to an improved sense amplifier circuitry for a MOS memory device.
2. Description of the Related Art
Recently, MOS dynamic random access memory (DRAM) devices are becoming more widely used in the manufacture of digital equipment, particularly small-size computers, as the speed and cost advantages of these devices increase. As semiconductor technology is advanced, the devices are increasing in integration density due to remarkable improvements in the memory cell structure and in the micro-fabrication techniques. As memory devices require higher packing density (integration density), higher speed, and lower dissipation, the sense amplifiers become critical.
Some prior DRAM devices employ what is called the "open bit-line" system that exhibits high integration density by allowing the area of memory cells to decrease on a chip substrate of limited size, while the others use the "folded bit-line" system which accomplishes an reduced sense-amplifier area and an enhanced noise-withstanding characteristics. A conflicting problem may exist in the two types of bit-line systems: While the open bit-line system is advantageous in the achievement of higher integration density of the memory cells, it suffers from the difficulty in designing sense-amplifier circuits to meet a strict circuit-design rule, which may results in that the positioning or distributing the sense amplifiers is difficult in a limited surface area of the substrate. In contrast, with the folded bit-line system, while the circuit design rule may become moderate to make it easier to design the sense amplifiers associated therewith, the integration density of memory cells decreases due to an increase in the required area of memory cells on the substrate.
Conventionally, with the open bit-line system, memory cells are allowed to be arranged at all the cross points as defined between the bit lines and the word lines; therefore, the resultant integration density of memory cells may be maximized, causing the memory-cell array section to decrease in occupation area on a chip substrate. On the other hand, in the open bit-line system, since two bit lines constituting each bit-line pair extend to run into two neighboring memory-cell subarrays, it is strictly required that a sense amplifier circuit associated therewith is packed within a reduced substrate-surface area, which may correspond in length to the bit-line width. Such a sense-amplifier layout requirement makes it difficult to arrange a number of sense amplifier circuits on the chip substrate as a whole.
Recently, to soften the layout difficulty, what is called the "relaxed open bit-line" system has been proposed, wherein sense amplifier circuits are alternately positioned on the both sides of a memory-cell subarray. However, even such a bit-line system will not able to meet sufficiently the demands for an further improvement in the integration density of DRAMs in the near future. Since a sense amplifier circuit should be required with respect to every group of two bit lines, the design rule for the sense amplifiers still remains strict as a whole.
In contrast, the folded bit-line system, which has been the major system for long in the DRAM technology since the past 64K-bit DRAM generation until today, uses bit-line pairs each consisting of two bit lines "folded" at their certain nodes on an one side thereof, whereat a corresponding sense amplifier circuit is electrically connected to the bit-line pair. Parallel word lines extend in a direction transverse to the two folded bit lines. Memory cells are arranged only at specifically selected ones of the cross points between the word lines and the bit lines, wherein the specific cross points are half the overall cross points in number. More specifically, looking at a single word line, only one of the two cross points as defined between this word line and the two folded bit lines is provided with a memory cell; any memory cell is prevented from bring arranged at the other of the two cross points. Looking at two neighboring word lines, the layout of memory cells may exhibit a "zig-zag" pattern. To attain such an arrangement, two sense amplifier circuits for two adjacent folded bit-line pairs are alternately located on the two opposite sides of a corresponding memory-cell subarray. This results in that, in a viewpoint of sense-amplifier circuit design, one sense amplifier may be provided with respect to four adjacent bit lines on one side of the subarray. This means that the positioning distance between sense amplifier circuits along the word-line direction can be allowed to increase substantially up to the width of four bit lines. It is thus possible to make easier the layout of a number of sense amplifier circuits on the chip substrate.
Unfortunately, with the presently available folded bit-line system, it cannot be permitted in principle that memory cells are arranged or distributed among all the cross points defined between the word lines and the bit lines, as has been described previously. This may cause the memory-cell array section to increase in area on the substrate surface as a whole. Such an increase in the area of the memory-cell array section will become a serious bar to the achievement of a further improved integration density in DRAMs. In particular, when the semiconductor technology is rushed into the age of extra-highly integrated DRAMs of the next generation (such as 256M-bit DRAMs or more), which will strictly require a further reduction in the cell-array area, it may be obvious that the folded bit-line system can no longer go with the trend of further improvements in the integration density. This can also be said due to the fact that the reduction in the area of each memory cell has approached almost the limit of inherence in the presently available DRAM devices.